Abu S Hassan

US Patent:

7437636, Oct 14, 2008

Filed:

Nov 1, 2005

Appl. No.:

11/265488

Inventors:

Janusz Rajski - West Linn OR, US
Abu Hassan - San Jose CA, US
Robert Thompson - Tualatin OR, US
Nagesh Tamarapalli - Wilsonville OR, US

International Classification:

G01R 31/28
G06F 11/00
G06F 1/04

US Classification:

714726, 714 30, 713503

Abstract:

Exemplary schemes for multi-frequency at-speed logic Built-In Self Test (BIST) are provided. For example, certain schemes allow at-speed testing of very high frequency integrated circuits controlled by a clock signal generated externally or on-chip. Some of the disclosed schemes are also applicable to testing of circuits with multiple clock domains which can be either the same frequency or different frequency. In particular embodiments, the loading and unloading of scan chains is separated from the at-speed testing of the logic between the respective domains and may be done at a faster or slower frequency than the at-speed testing. In certain embodiments, only the capture cycle is performed at the corresponding system timing. In some embodiments, a programmable capture window makes it possible to test every intra- and inter-domain at-speed without the negative impact of clock skew between clock domains.

US Patent:

20030097614, May 22, 2003

Filed:

Nov 20, 2002

Appl. No.:

10/301127

Inventors:

Janusz Rajski - West Linn OR, US
Abu Hassan - San Jose CA, US
Robert Thompson - Tualatin OR, US
Nagesh Tamarapalli - Wilsonville OR, US

Assignee:

Mentor Graphics Corporation

International Classification:

H02H003/05

US Classification:

714/030000

Abstract:

A scheme for multi-frequency at-speed logic Built-In Self Test (BIST) is provided. This scheme allows at-speed testing of very high frequency integrated circuits controlled by a clock signal generated externally or on-chip. The scheme is also applicable to testing of circuits with multiple clock domains which can be either the same frequency or different frequency. Scanable memory elements of the digital circuit are connected to define plurality of scan chains. The loading and unloading of scan chains is separated from the at-speed testing of the logic between the respective domains and may be done at a faster or slower frequency than the at-speed testing. The BIST controller, Pseudo-Random Pattern Generator (PRPG) and Multi-input Signature Register (MISR) work at slower frequency than the fastest clock domain. After loading of a new test pattern, a clock suppression circuit allows a scan enable signal to propagate for more that one clock cycle before multiple capture clock is applied. This feature relaxes the speed and skew constraints on scan enable signal design. Only the capture cycle is performed at the corresponding system timing. A programmable capture window makes it possible to test every intra- and inter-domain at-speed without the negative impact of clock skew between clock domains.